An SAR ADC is a type of ADC that converts an analog input signal into a digital representation by implementing a binary search algorithm. Via the binary search through possible quantization levels, the SAR ADC converges upon a digital output. An SAR ADC has been used for medium-to-high-resolution applications.
While the internal circuitry of the SAR ADC may be running at high frequency, the ADC sample rate is a fraction of that frequency due to the successive approximation algorithm. The resolution of SAR ADCs most commonly ranges from 8 to 16 bits, and they provide low power consumption as well as a small form factor. These features make the SAR ADCs desirable for a wide variety of applications, including mobile phones, etc.
Due to its benefits of high performance (e.g. achievable resolution and precision), low power consumption as well as low footprint, SAR ADCs became more and more popular in a communication system. The main disadvantage of the SAR ADCs is the limitation of the sampling frequency. This is due to the iterative nature of the SAR ADCs that convert one bit per cycle. The SAR ADC architectures require a clock frequency as follows:Fclock>R×Fsample,where Fclock is the operational clock frequency, R is the resolution of the SAR ADC in bits, and Fsample is the conversion or sampling frequency. In current deep submicron technologies, Fclock of 1 GHz is achievable, which means that for common precision requirements of 10 to 12 bits, a sampling frequency of 50 MHz is possible. Through time-interleaving this can be up-tuned by 2× or 4×, respectively, making this concept ideal for communication systems.